Performance Evaluation of AES using Hardware and Software Codesign

نویسندگان

  • Vilas V Deotare
  • Dinesh V Padole
  • Ashok S. Wakode
چکیده

Implementation of Advanced Encryption Standard (AES) algorithm is more intensive discussion from its starting publication especially in terms of performance. However the studies of implementation of AES using hardware or software, the performance and cost are high to low respectively. The propose method is implemented using hardware and software Co design. This paper presents AES implementation on different platform like ARM7, microblaze, FPGA and compares the results with these performances. The target hardware used in this paper is Spartan 3s400PQ208-4 FPGA from Xilinx. The performance is simulated and validated.

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تاریخ انتشار 2014